1. Field of the Invention
The invention relates to integrated circuits and, more particularly, to the routing of conductors in an integrated circuit to supply power and signals to circuitry therein.
2. Description of the Prior Art
Integrated circuits (xe2x80x9cIC""sxe2x80x9d) include circuitry which is typically organized in a hierarchical fashion of xe2x80x9ccellsxe2x80x9d and xe2x80x9cblocksxe2x80x9d of cells. Each cell will include a large plurality of circuit elements such as transistors, resistors and capacitors to carry out a particular elementary function. The cells are then grouped into circuit xe2x80x9cblocksxe2x80x9d, and the IC will have a large number of circuit blocks. IC""s use multiple levels of conductors for distributing power and signals from off the IC to the circuit blocks within the IC, between the circuit blocks, and between the cells within each circuit block.
The conductors are formed by lithographically patterning a layer of conductive material to form conductive lines as viewed from above the IC substrate. The conductive layers with conductive lines formed therein are separated by an insulating layer so that lines of one layer which cross another layer (when viewed from above) do not physically or electrically contact each other. When it is desired to electrically connect a conductor formed in one layer to a conductor formed in another layer, a conductive path is formed extending through the insulating layer between the two conductors. This conductive path is known in the integrated circuit art as a xe2x80x9cviaxe2x80x9d. The conductive layers are typically a metal, most commonly aluminum, but also include tungsten, copper and titanium and various alloys thereof Other materials are also known, such as metal suicides, metal nitrides and doped polysilicon. The insulating layer is commonly a dielectric material such as silicon dioxide.
The layers typically have different resistivities, with the lowest level (layer 1) having the highest resistivity and the highest level having the lowest resistivity. This is due to technological processing constraints such as smaller thickness at the lower layers. The different resistivities have influenced routing, with the higher resistivity, lower layers generally being used to make connections which are relatively close (e.g. within cells or blocks) while the higher level, lower resistivity layers are used to make longer connections, such as between points in different blocks.
The layout of the conductors has developed to a high degree and various software tools are available to automate the layout process with the input and guidance of the layout engineer. Factors which complicate and affect the layout include the impact of the chosen routing signal propagation with respect to signal timing between various cells and blocks, the impact of the routing on circuit density, and undesirable voltage drops along long conductor runs. The number of conductor layers also affects signal routing. As IC geometries have shrunk, the number of available layers has increased from three to five, and the number of layers commonly used is expected to further increase.
FIGS. 1-3 illustrate the layout of conductive lines in an integrated circuit employing five conductive layers according to a common approach. For sake of simplicity, and because the conductors need not be limited to metals, the conductive layers in which the conductive lines are formed will be referred to herein as xe2x80x9clayer 1xe2x80x9d, xe2x80x9clayer 2xe2x80x9d, xe2x80x9clayer 3xe2x80x9d, xe2x80x9clayer 4xe2x80x9d and xe2x80x9clayer 5xe2x80x9d. Layer 1 is closest to the substrate, with layers 1, 2 and 3 being referred to as xe2x80x9clow levelxe2x80x9d layers and layers 4 and 5 being referred to as xe2x80x9chigh level layersxe2x80x9d. Individual conductor lines, or simply xe2x80x9cconductorsxe2x80x9d, will bear reference numerals in the form xe2x80x9cXYYxe2x80x9d, with the digit X corresponding to the layer level in which that conductor resides. i.e. conductor 301 is in layer 3 and conductor 501 is in layer 5. Additionally, vias will be referred to with the legend xe2x80x9cXZYYxe2x80x9d, with the digits X and Z referring to the upper and lower, respectively, conductive layers which that via connects.
FIG. 1 is a top view of a standard cell 12. Within the cell 12 are numerous circuit elements as, discussed above. Along the opposing edges 12a, 12b of the cell are conductors 101, 103 lithographically formed from a layer 1. These horizontally extending conductors, known in the art as xe2x80x9crailsxe2x80x9d, are used to connect the cell 12 to a source of electric potential vdd! (rail 101) and to a lower source of potential, such as ground xe2x80x9cgnd!xe2x80x9d by rail 103. Connections between individual circuit elements as well as between circuit elements and the respective rail 101 or 103 may also be in layer 1.
FIG. 2 shows a portion of a xe2x80x9cblockxe2x80x9d of cells. FIG. 2A illustrates a top view, and FIG. 2B illustrates a side view corresponding to the cross-section AA in FIG. 2A. The block 20 includes cells 10, 11, 12, 13. In practice, a block of cells would typically include many more cells (such as one thousand cells). Generally speaking, each block of cells is xe2x80x9cself-containedxe2x80x9d in that it has input/output contacts in the form of conductive pads (xe2x80x9cpinsxe2x80x9d) which are connected to other blocks on the IC to electrically connect them together. Additionally, the blocks typically abut each other on all sides to maximize density. Here, the lower row of cells 10, 11 is bounded by another rail 105, in this case a power rail. Also shown, are conductors 202, 204, 206, 208 extending orthogonal to the rails 101, 103 and 105 and formed from a conductive layer 2 in a plane above and parallel to the layer 1 from which the rails 101-105 were formed. The conductors 202, 204, 206, 208 are known in the art as xe2x80x9cstripesxe2x80x9d and alternate in a similar manner as the rails with respect to connection to power (vdd!) and ground (gnd!). The ground stripes 204, 208 are connected to ground rail 103 by respective vias 2101 and 2102. The power stripes 202, 206 are connected to the power rails 101, 103 by respective vias 2103, 2104, 2105, 2106.
Typically, in a five layer system, the interconnection between blocks for signal routing is done in layer 5. Additionally, the power and ground conductors which distribute power across the IC from an off chip source of potential to the various blocks of cells are also in layer 5. The supply of power to the blocks, the supply of signals to and from the blocks, and the supply of signals between the blocks is known as the xe2x80x9ctop-levelxe2x80x9d design. Power and ground conductors at the cell level are in layer 1 while power and ground connections at the block level are in layers 2, 3, as illustrated in FIG. 2. Signal routing within a block is done in layers 3, 4. (not shown).
The layout design of an IC is typically done in a hierarchical fashion, starting from the cell level, moving to the block level and then the top level. The blocks are conventionally designed by a plurality of designers using the same software layout tools in a parallel fashion. When the block layouts are completed, the top level layout is then designed.
One problem with this layout approach of using conductors in layer 2 for power and ground delivery at the block level is that this allows access to the contact pins of each cell for from layer 1 only. Use of layer 1 for signal routing over anything more than very short distances makes it difficult to achieve proper signal timing because of its high resistivity. Cells cannot be placed under the layer 2 stripes 202, 204, 206, 208 of FIG. 2, because doing so would require the use of metal 1 for signal routing. FIG. 3 is a view of the area of block 20 around the stripes 202, 204. Instead of showing only four cells as in FIG. 2, FIG. 3 illustrates many more cells arranged in rows R1-RN. Under the stripes 202, 204 it is quite evident that there is significant chip area under these stripes which does not contain cells. This wasted space thus reduces the circuit density of the IC and increases its cost.
Conventionally, vias extend only vertically between layers, i.e. orthogonal to the stripes and rails. This poses a problem when trying to connect a top level power or ground conductor to a power/ground rail in layer 2, as it requires the use of xe2x80x9cstackedxe2x80x9d vias. A xe2x80x9cstackedxe2x80x9d via is a via that connects multiple layers. To connect from layer 5 to layer 2 requires a stack of three vias, i.e. a first via from a conductor in layer 5 to a conductor below it in layer 4, a second via from that conductor in layer 4 to a conductor below it in layer 3 and third via from the layer 3 conductor to a layer 2 conductor, with the vias being aligned. However, since the block level signal routing is in layers 3, 4, the stacked via cannot be put wherever there is an intervening signal conductor in layers 3, 4. One reason that this is problematic is that due to the bottom-up hierarchical design approach, the signal routing in layers 3, 4 is already in place before the top level designer starts routing the top level power and ground conductors. Another reason is that the sheer number of signal routing conductors in layers 3 and 4 does not leave much access area for the stacked vias necessary to connect layer 5 to layer 2. Thus, the large number of signal conductors in layers 3, 4 creates a pre-existing, tightly packed maze of signal conductors in these two layers between layers 5 and 2 that typically makes it impracticable to make subsequent connections from a power or ground conductor at the top level to an associated power or ground conductor in layer 2 at the block level.
One solution to this problem has been the use of xe2x80x9cringsxe2x80x9d each formed near the periphery of a block. FIG. 4 shows a top view of a portion of an integrated circuit showing a number of blocks 20, 21, 22, 23 each with a respective power rings 40, 41, 42, 43. Ring 40 includes conductors 210, 212 in layer 2 and conductors 311, 313 in layer 3. Ring 41 of block 21 includes conductors 214, 216, conductor 313 and conductor 315. Power rails 501, 503 bound the blocks at the upper and lower sides of the four blocks shown. Layer 4 stripes 402, 404, 406 extend between the power rails 501, 503. Vias connect the rails 501, 503 to the stripes 402, 404, 406. These level 4 stripes are connected to the rails 311, 313, 315 by vias, which level 3 rails are also connected with vias to the conductors 210, 212. In this manner, a power ring 40 is formed for block 20 by the conductors 210, 212 and the portions of the conductors 311, 313 between conductors 210, 212, and this ring is connected to vdd! by the rails 501, 503 and conductors 402, 404. The other rings 41, 42, 43 are connected to the supply potential vdd! in a similar manner. Power would be distributed to the individual cells from the ring 41, for example, by dropping vias from the conductors 210, 212 to the level 1 rails running along the cell edge as in FIG. 1. In FIG. 4, only the power ring is shown. A corresponding ground ring would be adjacent each of the power rings 41-43, for example inside or outside of these power rings.
One problem with the use of rings is that power is generally not distributed evenly to the cells within a block because the cells are not equally spaced from the ring. Cells near the middle of the block are further away than cells near the periphery of the block. More even distribution could be achieved by adding more layer 2 stripes, but because cells cannot be placed under layer 2 power or ground conductors as already discussed, such additional layer 2 conductors would merely exacerbate the loss of cells in the block and even further reduce circuit density.
According to the invention, the above disadvantages of the prior art are overcome in an integrated circuit having a plurality of cells of circuit elements defining a cell layer, conductors disposed in a plurality of layers adjacent the cell layer, and vias connecting conductors in a layer to conductors in other layers. The number of layers of conductors is N, N being four or greater, the first layer being next to the cell level and the Nth layer being remote from the cell level. Each cell has a cell border and is connected to a respective power and ground conductor in a first layer adjacent the cell border. Power and ground conductors extend across the cells in at least one of the N and N-1 layers and stacked vias connect the power and ground conductors of the at least one of N and N-1 layers to respective power and ground conductors of the first layer.
Placement of the block level power and ground conductors in the top two layers of conductors, instead of in the lower level layers has been found to significantly increase circuit density. This is primarily due to the ability to place cells under the high level layer, power and ground conductors, avoiding the cell loss problem under layer 2 power and ground conductors as in the prior art. Additionally, power and ground rings in low level layers and their attendant disadvantages are avoided.
Another aspect of the invention concerns a method of laying out the conductors of an IC to place the block level power and ground conductors in the high level conductor layers.
Yet another aspect of the invention concerns a method of laying out the conductors of an IC by placing signal routing, power or ground conductors within the lower level layers in dependence on the prior designation of the placement of the power or ground conductors for the block and top levels in the top level layers. Favorably, a grid of power and ground conductors is placed at the top level which defines the size and placement of blocks of cells on the IC. Also, the signal routing conductors may be placed after placement of the vias which connect the top level power and ground conductors to the first level power and ground conductors. Generally speaking, this method is a top-down approach, as opposed to the commonly used bottom-up approach, and places priority on layout of the power supply conductors over that of signal routing conductors. In addition to increased circuit density, the inventors have found this approach reduces the design cycle as well, as it is easy to connect block level power and ground conductors to the top level power and ground conductors. There is no need to make connections from all the four sides of the block at the top level, which consumed a significant amount of time within the prior approach.
These and other object, features and advantages of the invention will become apparent with reference to the following detailed description and the drawings.